Fifo verilog code basic6/9/2023 What I'm struggling with is how to place this data in the FIFO on every pixel clock pulse, and incrementing the SDRAM address at the same time/clock pulse. The SDRAM works on a 100mhz clock, thats why in between I got an Asynchronous FIFO to handle the differents in clock speeds. The basic concept I want to achieve is a 'video frame buffer', the input is a 15bit RGB signal with a pixel clock of around 2.3mhz the 5 bits deep data needs to be converted to 8 bits deep and stored on the SDRAM. For this reason working with FPGA is new for me, and I can say it hasn't been the smoothest of roads for me There are a few concepts I'm really struggling with, so I hope somebody could help me out. Hi everyone, let me preface by saying I'm a software engineer by day, and a hobbyist by night.
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